1. Field of the Invention
The present invention generally relates to semiconductor memory, and more particularly to a 3-transistor-2-capacitor (3T2C) dynamic random access memory (DRAM) cell.
2. Description of Related Art
Semiconductor memory is one of the most commonly used data storage media. Examples of the semiconductor memory include, among others, dynamic random access memory (DRAM) and static random access memory (SRAM). The semiconductor memory itself may be manufactured as an integrated circuit, or may be integrated with other components to form, for example, a system on chip (SOC).
For modern SOC applications, a substantial portion, e.g., 60% to 70%, of the circuit area is dedicated to the memory. The selection of the type and technology of the memory thus plays an important role in the overall performance and cost in the entire chip.
Some SOCs employ DRAM technology in forming the data storage media. FIG. 1A schematically shows one conventional DRAM cell, which includes a storage capacitor Cs and an access transistor Ta. Due to its simple structure, DRAM has higher density, for example, than SRAM. However, the conventional DRAM need be fabricated in a specific manufacturing process in order to enlarge the capacitance of the storage capacitor Cs with small silicon area. Such specific manufacturing process is, unfortunately, not compatible with the SOC process, therefore increasing the overall fabrication cost.
Some other SOCs employ SRAM technology in forming the data storage media. FIG. 1B schematically shows one conventional SRAM cell, which includes two cross-coupled inverters 10 and two access transistors Tb and Tc. Unlike DRAM, SRAM has a manufacturing process that is generally compatible with the SOC process, but has lower density than DRAM. Further, as shown in FIG. 1B, due to the fact that the cross-coupled inverters 10 are directly coupled to power Vdd and ground, the SRAM cell is thus prone to power-incurred noise.
Accordingly, a need has arisen to propose a novel memory structure that may be fabricated, for example, in standard complementary-metal-oxide-semiconductor (CMOS) process to reduce the fabrication cost, while the high density may be also substantially maintained.